Home
>
Archives
>
RSD (Archive)
>
Obsolete
>
Rigorous Design of Component-Based Systems — The BIP (…)
>
BIP Tools
The Language Factories
Sommaire
Overview
, p1
MATLAB/Simulink to BIP
, p2
C to BIP
, p3
DOL to BIP
, p4
Distribution
, p4
System Requirements
, p4
Installing the Toolchain
, p4
Coding guidelines for process
, p4
Running an example
, p4
Case Studies
, p5
1
2
3
4
5
Case Studies
MJPEG Decoder
1
2
3
4
5
Browsing
Sections
Verimag
Topics
Contact
Site Map
Building Access
News
NEWS
Cybersécurité, sûreté et programmation
Poste de Professeur⋅e des Universités Verimag/UGA
Intelligence artificielle, sciences du logiciel, méthodes formelles
Poste de Professeur⋅e des Universités Verimag/Grenoble-INP
Seminars
Seminars
2 April 2026
Mohamed Graiet:
Approche formelle générique de transfert learning (gtl) dans le continuum cei
New publications
Some Recent Publications
Akram Idani, Yves Ledru, German Vega:
Formal model-driven security combining B-method and process algebra: The B4MSecure platform
Marius Bozga, Radu Iosif, Arnaud Sangnier, Neven Villani:
Counting Abstraction and Decidability for the Verification of Structured Parameterized Networks
Iulia Dragomir, Carlos Redondo, Tiago Jorge, Laura Gouveia, Iulian Ober, Marius Bozga, Maxime Perrotin:
Specification and model-checking of space systems in the TASTE toolset
Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian:
Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance vs. Precision Trade-offs
Jobs and internships
Jobs and internships
Poste de Professeur⋅e des Universités Verimag/Grenoble-INP
Poste de Professeur⋅e des Universités Verimag/UGA
[PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
[Thèse] Contre-mesures logicielles “flot de données” pour la sécurité de bout-en-bout
Contact
|
Site Map
|
Site powered by SPIP 4.4.13
+
AHUNTSIC
[CC License]
info visites
5804010
English
Français