@incollection{Moy05b,
title = { Chapter 5.9, Formal Verification },
author = {Moy, Matthieu},
year = {2005},
booktitle = {Transaction-Level Modeling with {SystemC}. {TLM} Concepts and Applications for Embedded Systems},
pages = {190--206},
publisher = {Springer},
team = {SYNC},
}
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- November 24-28 2025 Synchron 2025
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- 13 November 2025 Yann Herklotz: Towards scalable verification and efficient hardware generation using verified (…)
- 21 November 2025 Oussama Oulkaid: Formal models of integrated circuits for transistor level electrical verification (Phd)
- 25 November 2025 Véronique Cortier: Electronic voting: design, attack, and formal verification
- 1 December 2025 Sylvain Boulme: Introduction à la programmation orientée objet en crystal
- 4 December 2025 Jannik Laval: A venir (thème cybersécu)
- 11 December 2025 Thaïs Baudon: A venir (thème: compilation optimisant les représentations mémoire)
New publications
- Some Recent Publications
- Karine Altisen, Marius Bozga: Revisited Convergence of a Self-stabilizing BFS Spanning Tree Algorithm
- Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes: On Self-stabilizing Leader Election in Directed Networks
- Thomas Vigouroux, Marius Bozga, Cristian Ene, Laurent Mounier: Function Synthesis for Maximizing Model Counting
- Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian: Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance Versus Precision Tradeoffs
Jobs and internships
- Jobs and internships
- [Funded PhD] Fault Injection Attacks: Automated Analysis of Counter-Measures At The Binary Level
- [Master] Decision Procedure for Equivalence Relations
- [Master]Leakage in presence of an active and adaptive adversary
- [PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences