@phdthesis{Mai08,
title = { Modeliser la prediction de branchement pour le calcul de temps d'execution pire-cas },
author = {Maiza-Burgui\`ere, Claire},
month = {june},
year = {2008},
school = {Universite Paul Sabatier - Toulouse 3},
team = {IRIT-TRACES},
}
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- Conferences
- November 24-28 2025 Synchron 2025
Seminars
- Seminars
- 13 November 2025 Yann Herklotz: Towards scalable verification and efficient hardware generation using verified (…)
- 21 November 2025 Oussama Oulkaid: Formal models of integrated circuits for transistor level electrical verification (Phd)
- 25 November 2025 Véronique Cortier: Electronic voting: design, attack, and formal verification
- 1 December 2025 Sylvain Boulme: Introduction à la programmation orientée objet en crystal
- 4 December 2025 Jannik Laval: A venir (thème cybersécu)
- 11 December 2025 Thaïs Baudon: A venir (thème: compilation optimisant les représentations mémoire)
New publications
- Some Recent Publications
- Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes: Self-stabilizing synchronous unison in directed networks
- Thomas Vigouroux, Marius Bozga, Cristian Ene, Laurent Mounier: Function Synthesis for Maximizing Model Counting
- Marius Bozga, Radu Iosif, Arnaud Sangnier, Neven Villani: Counting Abstraction and Decidability for the Verification of Structured Parameterized Networks
- Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne: A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
Jobs and internships
- Jobs and internships
- [Funded PhD] Fault Injection Attacks: Automated Analysis of Counter-Measures At The Binary Level
- [Master] Decision Procedure for Equivalence Relations
- [Master]Leakage in presence of an active and adaptive adversary
- [PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences